As the integrated circuit (IC) technology advances, the transistor device dimension is shrank and the power supply voltage is reduced. The digital circuitry benefits on the lower power consumption with the reduced supply. However the analog circuitry design is more difficult with the reduced supply since the voltage headroom is limited. In today's system-on-a-chip (SoC) integrated circuit, it consists of at least two supplies voltages; the higher analog supply is used for input/output (IO) and analog circuitry such as Radio Frequency (RF) circuit or Intermediate Frequency (IF) circuit while the lower digital supply is mainly used for digital circuitry such as digital filtering and signal processing function. FIG. 1 illustrates a common block diagram of communication system-on-a-chip (SoC) integrated circuit. Analog domain 101 consists of RF, IF and ADC while Digital domain 102 consists of digital baseband and DSP functional blocks. Analog-to-digital converter (ADC) sits in between and serves as the boundary of analog circuit domain and digital circuit domain. Conventionally analog supply is applied to ADC for achieving better performance. However, to further reduce the power consumption especially for mobile or portable applications, ADC is forced to use lower supply and is moved from analog domain into digital domain as illustrated on FIG. 2. By operating on a lower supply, ADC's input full-scale range has to be reduced. Nevertheless, Intermediate Frequency (IF) stage outputs range is not reduced to maintain decent performance metrics. In this case, the IF stage output range is greater than ADC's allowable input full-scale range.
The common approach to solve this issue is adding one more stage before ADC to reduce the signal range. This extra stage can be a continuous-time type gain amplifier as illustrated on FIG. 3 or discrete-time sampled based Sample and Hold (S/H) as illustrated on FIG. 4. An inverting amplifier 302 in FIG. 3 reduces Intermediate Frequency 301 output voltage to fit ADC 303 input range. In FIG. 4, Sample and Hold 402 samples Intermediate Frequency 401 output and produces a lower output range into ADC 403. The drawback of adding a gain amplifier like 302 is the increase of noise mainly due to the resistor's R1 and R2 thermal noise. And the drawback of adding a Sample and Hold (S/H) like 402 is the degradation of linearity. Since Sample and Hold is driving the sampling capacitor Csample of pipelined ADC, obtaining a good linearity is quite challenging due to the large sampling capacitor loading. The extra power consumption of either a gain amplifier or Sample and Hold is also disadvantageous.
The presented invention solves this over range input issue and achieves good noise and linearity performance without adding extra stage and power consumption. A more complete appreciation of the present invention and its improvements can be obtained by referring to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.